In the field of micro-technology, if it is a question of producing electronic, optical or opto-electronic components, or even micro-mechanical components (for example micro-accelerators), silicon substrates are often used, but it must be clearly understood that other materials are equally usable, often other semiconductor materials, formed of elements from column IV of the periodic table of the elements (especially germanium and its alloys with silicon), columns III-V of that table (especially GaAs or InP), or even columns II-VI of that table, even LiNbO3, SiC, diamond, and the like.
The use, and more particularly the production, of such hybrid substrates, whether the mixed layer is buried or on the surface, is of interest for diverse applications, especially MOS type devices.
In this latter case, given the limitations of MOSFET devices in terms of performance, the change of the crystalline orientation of the surface of the substrate used (mostly Si), just like the change of the direction of the conduction channel of the transistors, appears as a simple and effective solution. Many studies have demonstrated the impact of the orientation of the free surface and the direction of the conduction channel on the respective mobilities of holes and electrons. Thus improving the mobility of the carriers (holes) can be obtained via the use of a free surface of orientation <110> in comparison with a standard free surface of type <100>, as recently reported by Yang et al. (see reference 1 below). However, the CMOS technology is based on the simultaneous use of n-MOS type transistors (conduction by electrons) and p-MOS type transistors (conduction by holes). Furthermore, a change of the orientation of the surface has antagonistic effects on the electrons and on the holes, thus necessitating two free surface orientations, different for these two types of carrier. Thus it is necessary to be able to produce and to make cohabit two types of orientation on the same substrate.
Clearly, depending on the intended applications, the hybrid layer can extend along an electrically insulative layer or not.
Techniques for production of hybrid structures are already known.
See, for example, PCT patent publication No. WO-2004/059711 or its US equivalent U.S. patent publication No. 2006/0166461, which proposes the formation of a mixed or hybrid structure by molecular bonding of two substrates one of which has on its surface two types of areas differing in terms of their constituent materials; in the above document, these two types of areas are obtained by techniques of lithography, etching, thermal oxidation of the surface and polishing so that thermal oxide remains only in etched areas. An improvement on this technique is proposed in the European patent publication No. EP-1 923 912 or its US equivalent U.S. patent publication No.-2008/0079123, which teaches the formation of a sacrificial layer guaranteeing the flatness of the surfaces finally laid bare.
Moreover, the article “High Performance CMOS Fabricated on Hybrid Substrate With Different Crystal Orientations” by Yang, leong, Shi, Chan, Chan, Chou, Gusev, Jenkins, Boyd, Ninomiya, Pendleton, Surpris, Heenan, Ott, Guarini, D'Emic, Cobb, Mooney, To, Rovedo, Benedict, Mo, Ng, published in IEDM 03-2003 pp. 453-456 proposes, instead of using thermal oxidation to fill the etched areas, excavation by etching of cavities in an SOI substrate (in particular, one with a semiconductor layer on top of a buried electrically insulative layer), through the insulative layer, and to cause these cavities to be filled epitaxially from the bottom of these etched areas, which consists of a material (under this insulative layer) chosen to have a different crystallography to unetched areas. This technique is discussed in more detail in “Hybrid-Orientation Technology (HOT); Opportunities and Challenges” by Yang, Chan, Chan, Shi, Fried, Stathis, Chou, Gusev, Ott, Burns, Fischetti, leong published in IEEE Transaction on Electron Devices, Vol. 53, No. 5, May 2006, pp. 965-978.
In another article, Yang et al. have shown through simulation the importance of providing a buried continuous electrical insulator under the areas with different orientations and have proposed a modification of their production method (as defined in reference 2) aiming to minimize interruptions of the electrically insulative buried layer; this modification consists in providing for the etching through the electrically insulative buried layer to be effected over a section smaller than that of the cavity excavated in the layer situated on top of this insulative layer. “Silicon-on-isolator MOSFETs with Hybrid Crystal Orientations” by Yang, Chan, Kumar, Lo, Sleight, Chang, Rao, Bedell, Ray, Ott, Patel, D'Emic, Rubino, Zhang, Shi, Steen, Sikorski, Newbury, Meyer, To Kozlowski, Graham, Maurer, Medd, Canaperi, Deligianni, Tornello, Gibson, Dalton, leong, Shabidi published in Symposium on VLSI Technology Digest of Technical Papers, 2006.
It is nevertheless clear that epitaxial deposition is a technique subject to relatively strict operating constraints, which sometimes generates a significant cost.
Another production technique is described by Yin et al.; this technique is based on using a DSB (Direct Silicon Bonding) structure, that is to say one obtained by direct bonding of two silicon substrates with different crystalline orientations: by lithography and ion implantation, areas of one of the substrates are selectively rendered amorphous throughout its thickness as far as the interface between the two substrates, and the areas rendered amorphous are caused to recrystallize according to the crystallography of the other substrate; it is stated that unless, before recrystallization, trenches are formed between the areas rendered amorphous and the areas that have not been rendered amorphous, two competing recrystallization phenomena are observed, starting from the underlying substrate (with a first crystal orientation) and starting from adjacent areas (with another crystal orientation). “Direct Silicon Bonded (DSB) Substrate Solid Phase Epitaxy (SPE) Integration Scheme Study for High Performance Bulk CMOS” by Yin, Sung, Ng, Saenger, Chan, Crowder, Zhang, Li, Ott, Pfeiffer, Bendernagel, Ko, Ren, Chen, Wang, Liu, Cheng, Mesfin, Kelly, Ku, Luo, Rovedo, Fogel, Sadana, Khare, Shahidi, published in 1-4244-0439-8/06/$20.00 © 2006 IEEE
This principle of solid phase recrystallization appears to have significant advantages, especially in terms of cost, relative to the epitaxial technique, but it is therefore clear that using a mixed layer for fabrication does not achieve precise control of the microstructure of the areas initially amorphous near the other areas; the final geometry of the initially amorphous areas of the mixed layer depends, unless trenches are provided between the adjacent areas, on competition between tangential recrystallization starting from “other” areas and vertical crystallization starting from the underlying substrate, which can lead to involuntary trapezoids. More generally, it can be important to be able to guarantee that the mixed layer has substantially the same geometry and/or the same structure in terms of lower and upper edges as those other areas.